Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12166110 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2024-12-10 |
| 12148721 | Iterative formation of damascene interconnects | Sean P. Kilcoyne, Michael V. Liguori, Michael J. Rondon | 2024-11-19 |
| 12107132 | Source/drain contact positioning under power rail | Ruilong Xie, Indira Seshadri, Kangguo Cheng | 2024-10-01 |
| 12080559 | Using a same mask for direct print and self-aligned double patterning of nanosheets | Stuart A. Sieg, Daniel James Dechene | 2024-09-03 |
| 12021135 | Bottom source/drain etch with fin-cut-last-VTFET | Tao Li, Indira Seshadri, Nelson Felix | 2024-06-25 |
| 12002805 | Local vertical interconnects for monolithic stack transistors | Heng Wu, Ruilong Xie, Chen Zhang | 2024-06-04 |
| 11973125 | Self-aligned uniform bottom spacers for VTFETS | Ruilong Xie, Hemanth Jagannathan, Jay William Strane | 2024-04-30 |
| 11916013 | Via interconnects including super vias | Yann Mignot, Christopher J. Waskiewicz, Chanro Park | 2024-02-27 |
| 11869936 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Robert R. Robison, John R. Sporre +1 more | 2024-01-09 |
| 11869937 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Robert R. Robison, John R. Sporre +1 more | 2024-01-09 |