| 12176249 |
3D nano sheet method using 2D material integrated with conductive oxide for high performance devices |
H. Jim Fulford, Partha Mukhopadhyay |
2024-12-24 |
| 12170326 |
Three-dimensional device with vertical core and bundled wiring |
H. Jim Fulford |
2024-12-17 |
| 12148668 |
Stackable semiconductor device with 2D material layer and methods of manufacturing thereof |
H. Jim Fulford |
2024-11-19 |
| 12133387 |
3D memory with conductive dielectric channel integrated with logic access transistors |
H. Jim Fulford, Partha Mukhopadhyay |
2024-10-29 |
| 12131956 |
Ultra dense 3D routing for compact 3D designs |
H. Jim Fulford, Partha Mukhopadhyay |
2024-10-29 |
| 12114480 |
Method of making of plurality of 3D vertical logic elements integrated with 3D memory |
H. Jim Fulford, Partha Mukhopadhyay |
2024-10-08 |
| 12087640 |
High density logic formation using multi-dimensional laser annealing |
H. Jim Fulford, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame |
2024-09-10 |
| 12087817 |
High performance 3D vertical transistor device enhancement design |
H. Jim Fulford |
2024-09-10 |
| 12068205 |
3D high density compact metal first approach for hybrid transistor designs without using epitaxial growth |
H. Jim Fulford, Partha Mukhopadhyay |
2024-08-20 |
| 12040236 |
3D devices with 3D diffusion breaks and method of forming the same |
H. Jim Fulford |
2024-07-16 |
| 12020990 |
Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks |
Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, H. Jim Fulford +1 more |
2024-06-25 |
| 12009355 |
3D stacked DRAM with 3D vertical circuit design |
H. Jim Fulford, Partha Mukhopadhyay |
2024-06-11 |
| 12002809 |
Method to enhance 3D horizontal nanosheets device performance |
H. Jim Fulford |
2024-06-04 |
| 12001147 |
Precision multi-axis photolithography alignment correction using stressor film |
Daniel Fulford, Anthony R. Schepis, Anton J. deVilliers, H. Jim Fulford |
2024-06-04 |
| 11978735 |
Transistor stack of vertical channel ferroelectric FETs and methods of forming the transistor stack |
Robert D. Clark, H. Jim Fulford |
2024-05-07 |
| 11942536 |
Semiconductor device having channel structure with 2D material |
Robert D. Clark, H. Jim Fulford |
2024-03-26 |
| 11908747 |
Method for designing three dimensional metal lines for enhanced device performance |
H. Jim Fulford |
2024-02-20 |
| 11894378 |
Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance |
H. Jim Fulford |
2024-02-06 |
| 11887897 |
High precision 3D metal stacking for a plurality of 3D devices |
H. Jim Fulford |
2024-01-30 |
| 11876125 |
Method of making a plurality of high density logic elements with advanced CMOS device layout |
H. Jim Fulford |
2024-01-16 |