Issued Patents 2023
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11844223 | Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-12-12 |
| 11841757 | Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-12-12 |
| 11829699 | Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-11-28 |
| 11823725 | Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-11-21 |
| 11816036 | Method and system for performing data movement operations with read snapshot and in place write update | Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more | 2023-11-14 |
| 11791233 | Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-10-17 |
| 11790969 | Apparatus and method for endurance of non-volatile memory banks via outlier compensation | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-10-17 |
| 11694940 | 3D stack of accelerator die and multi-core processor die | Amrita Mathuriya, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-07-04 |
| 11670352 | Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-06-06 |