Issued Patents 2023
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11855223 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani | 2023-12-26 |
| 11749733 | FIN shaping using templates and integrated circuit structures resulting therefrom | Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar | 2023-09-05 |
| 11742410 | Gate-all-around integrated circuit structures having oxide sub-fins | Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar | 2023-08-29 |
| 11721580 | 1D vertical edge blocking (VEB) via and plug | Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward, Richard E. Schenker +4 more | 2023-08-08 |
| 11715775 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar | 2023-08-01 |
| 11594637 | Gate-all-around integrated circuit structures having fin stack isolation | Stephen D. Snyder, Biswajeet Guha, William Hsu, Urusa Alaan, Tahir Ghani +4 more | 2023-02-28 |
| 11594448 | Vertical edge blocking (VEB) technique for increasing patterning process margin | Chul-Hyun Lim, Paul A. Nyhus, Elliot N. Tan, Charles H. Wallace | 2023-02-28 |
| 11581315 | Self-aligned gate edge trigate and finFET devices | Szuya S. Liao, Biswajeet Guha, Tahir Ghani, Christopher KENYON | 2023-02-14 |
| 11569231 | Non-planar transistors with channel regions having varying widths | Stephen D. Snyder, Richard E. Schenker, Michael K. Harper, Sam Sivakumar, Urusa Alaan +2 more | 2023-01-31 |
| 11569370 | DEPOP using cyclic selective spacer etch | Vivek Thirtha, Shu Zhou, Nitesh Kumar, Biswajeet Guha, William Hsu +4 more | 2023-01-31 |