Issued Patents 2022
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11342326 | Self-aligned etch in semiconductor devices | Yi-Hsun Chiu, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang | 2022-05-24 |
| 11276695 | Multi-gate device and related methods | Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang | 2022-03-15 |
| 11271094 | Semiconductor structure and method of manufacturing the same | Chi-Yi Chuang, Kuan-Lun Cheng, Chih-Hao Wang | 2022-03-08 |
| 11264508 | Leakage prevention structure and method | Yi-Bo Liao, Sai-Hooi Yeong, Hou-Yu Chen, Yu-Xuan Huang, Kuan-Lun Cheng | 2022-03-01 |
| 11257903 | Method for manufacturing semiconductor structure with hybrid nanostructures | Wen-Ting Lan, Guan-Lin Chen, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang +1 more | 2022-02-22 |
| 11251308 | Semiconductor device and method | Yi-Bo Liao, Yu-Xuan Huang, Pei-Yu Wang, Cheng-Ting Chung, Hou-Yu Chen | 2022-02-15 |
| 11245029 | Structure and formation method of semiconductor device with metal gate stack | Wang-Chun Huang, Kuan-Lun Cheng, Chih-Hao Wang | 2022-02-08 |
| 11227932 | FinFET devices with a fin top hardmask | Kuo-Cheng Ching, Kai-Chieh Yang, Kuan-Lun Cheng, Chih-Hao Wang | 2022-01-18 |
| 11227917 | Nano-sheet-based devices with asymmetric source and drain configurations | Cheng-Ting Chung, Yu-Xuan Huang, Yi-Bo Liao, Kuan-Lun Cheng | 2022-01-18 |
| 11222958 | Negative capacitance transistor with external ferroelectric structure | Chi-Hsing Hsu, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao | 2022-01-11 |
| 11217484 | FinFET gate structure and related methods | Cheng-Ting Chung, Kuan-Lun Cheng | 2022-01-04 |