Issued Patents 2021
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211469 | Third generation flash memory structure with self-aligned contact and methods for forming the same | Jhih-Bin Chen | 2021-12-28 |
| 11209673 | Heater structure configured to improve thermal efficiency in a modulator device | Shih-Wei Lin | 2021-12-28 |
| 11183571 | Memory device and manufacturing method thereof | Yong-Sheng Huang, Chih-Ren Hsieh | 2021-11-23 |
| 11164844 | Double etch stop layer to protect semiconductor device layers from wet chemical etch | Chen Chen, Eugene Chen | 2021-11-02 |
| 11158593 | Structures for bonding a group III-V device to a substrate by stacked conductive bumps | Jhih-Bin Chen, Chia-Shiung Tsai, Eugene Chen | 2021-10-26 |
| 11158797 | RRAM cell structure with conductive etch-stop layer | Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai | 2021-10-26 |
| 11158789 | Leakage resistant RRAM/MIM structure | Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai | 2021-10-26 |
| 11158648 | Double channel memory device | Hung-Shu Huang | 2021-10-26 |
| 11152384 | Boundary structure for embedded memory | Harry-Hak-Lay Chuang, Shih-Chang Liu | 2021-10-19 |
| 11143817 | Semiconductor structure and manufacturing method of the same | Yung-Chang Chang, Chung-Yen Chou, Shih-Chang Liu | 2021-10-12 |
| 11103725 | Wireless optogenetic device and associated radiation system | Peng Shi, Xudong Lin | 2021-08-31 |
| 11107825 | Flash memory structure with enhanced floating gate | Hung-Shu Huang | 2021-08-31 |
| 11069873 | Formation of a two-layer via structure to mitigate damage to a display device | Yung-Chang Chang | 2021-07-20 |
| 11025033 | Bump bonding structure to mitigate space contamination for III-V dies and CMOS dies | Jhih-Bin Chen | 2021-06-01 |
| 11005037 | Leakage resistant RRAM/MIM structure | Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai | 2021-05-11 |
| 10998450 | Memory device and manufacturing method thereof | Yong-Sheng Huang | 2021-05-04 |
| 10985090 | Methods of manufacturing a thin film resistor with ends overlapped by interconnect pads | Yuan-Tai Tseng, Chia-Shiung Tsai, Chung-Yen Chou | 2021-04-20 |
| 10903366 | Forming fin-FET semiconductor structures | Sheng-Chieh Chen | 2021-01-26 |
| 10896985 | Dielectric sidewall structure for quality improvement in GE and SIGE devices | Chih-Ming Chen, Lee-Chuan Tseng, Po-Chun Liu | 2021-01-19 |