Issued Patents 2021
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11108526 | Channel quality indicator (CQI) reporting for ultra-reliable low latency communications (URLLC) | Gabi Sarkis, Jing Jiang, Wanshi Chen, Wei Yang, Chih-Ping Li | 2021-08-31 |
| 11096186 | Modulation and coding scheme table design for power efficiency | Jing Jiang, Joseph Binamira Soriaga, Gabi Sarkis, Peter Pui Lok Ang, Jing Lei | 2021-08-17 |
| 11093058 | Single layer sensor pattern and sensing method | Qingbiao Deng, Sang Chul Han, Yi Zhang | 2021-08-17 |
| 11089598 | Multiple access signatures for non-orthogonal multiple access (NOMA) wireless communications | Jing Lei, Gabi Sarkis, Joseph Binamira Soriaga, Wanshi Chen, Seyong Park +1 more | 2021-08-10 |
| 11057051 | Fractally enhanced kernel polar coding | Jing Jiang, Wei Yang, Gabi Sarkis, Jing Lei, Seyong Park | 2021-07-06 |
| 11031958 | Hybrid polar code design for ultra-reliable low latency communications (URLLC) | Jing Jiang, Yang Yang, Gabi Sarkis, Joseph Binamira Soriaga | 2021-06-08 |
| 11031360 | Techniques for an inductor at a second level interface | Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji-Yong Park, Srinivas V. Pietambaram +3 more | 2021-06-08 |
| 11005595 | Self-decodability for low-density parity-check codes | Jing Jiang, Gabi Sarkis, Yang Yang | 2021-05-11 |
| 10972219 | LDPC interleaver design for improved error floor performance | Jing Jiang, Gabi Sarkis, Joseph Binamira Soriaga, Jing Lei, Seyong Park | 2021-04-06 |
| 10972217 | Scheduling for low-density parity-check codes | Jing Jiang, Peter J. Black, Joseph Binamira Soriaga, Gabi Sarkis | 2021-04-06 |
| 10966231 | Configuring aggregation level and physical downlink control channel candidates at a user equipment | Huilin XU, Peter Pui Lok Ang | 2021-03-30 |