Issued Patents 2021
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11177385 | Transistors with a hybrid source or drain | Haiting Wang, Sipeng Gu, Baofu Zhu | 2021-11-16 |
| 11171237 | Middle of line gate structures | Yanping Shen, Halting Wang, Hui Zang | 2021-11-09 |
| 11145716 | Semiconductor devices with low resistance gate structures | Rinus Tek Po Lee | 2021-10-12 |
| 11127834 | Gate structures | Sipeng Gu, Halting Wang | 2021-09-21 |
| 11121023 | FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin | Hong Yu, Jinping Liu, Hui Zang | 2021-09-14 |
| 11114466 | IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products | Sipeng Gu, Haiting Wang | 2021-09-07 |
| 11094598 | Multiple threshold voltage devices | Bharat Krishnan, Rinus Tek Po Lee, Hyung-yoon Choi | 2021-08-17 |
| 11075298 | LDMOS integrated circuit product | Judson R. Holt, Sipeng Gu, Halting Wang | 2021-07-27 |
| 11075268 | Transistors with separately-formed source and drain | Baofu Zhu, Haiting Wang, Sipeng Gu | 2021-07-27 |
| 11043566 | Semiconductor structures in a wide gate pitch region of semiconductor devices | Judson R. Holt, Sipeng Gu, Haiting Wang | 2021-06-22 |
| 11031389 | Semiconductor structures over active region and methods of forming the structures | Hui Zang | 2021-06-08 |
| 11004953 | Mask-free methods of forming structures in a semiconductor device | Rinus Tek Po Lee, Hui Zang, Hong Yu, Wei Hong | 2021-05-11 |
| 11004748 | Semiconductor devices with wide gate-to-gate spacing | Sipeng Gu, Haiting Wang | 2021-05-11 |
| 10971583 | Gate cut isolation including air gap, integrated circuit including same and related method | Hong Yu, Hui Zang | 2021-04-06 |
| 10964599 | Multi-step insulator formation in trenches to avoid seams in insulators | Asli Sirman, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu | 2021-03-30 |
| 10943814 | Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through | Ryan Sporer | 2021-03-09 |
| 10937685 | Diffusion break structures in semiconductor devices | Sipeng Gu, Haiting Wang | 2021-03-02 |
| 10923469 | Vertical resistor adjacent inactive gate over trench isolation | Hui Zang, Guowei Xu, Ruilong Xie, Yurong Wen, Garo Derderian +2 more | 2021-02-16 |
| 10896853 | Mask-free methods of forming structures in a semiconductor device | Rinus Tek Po Lee, Wei Hong, Hui Zang, Hong Yu | 2021-01-19 |