Issued Patents 2021
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11210586 | Weight value decoder of neural network inference circuit | Kenneth Duong, Jung Ko | 2021-12-28 |
| 11205115 | Neural network inference circuit | Kenneth Duong, Jung Ko | 2021-12-21 |
| 11176450 | Three dimensional circuit implementing machine trained network | Kenneth Duong | 2021-11-16 |
| 11170289 | Computation of neural network node by neural network inference circuit | Kenneth Duong, Jung Ko | 2021-11-09 |
| 11163069 | Differential correction map for GNSS | Brian W. Kroeger, Paul J. Peyla | 2021-11-02 |
| 11163986 | Using batches of training items for training a network | Eric A. Sather, Andrew C. Mihal | 2021-11-02 |
| 11151695 | Video denoising using neural networks with spatial and temporal features | Andrew C. Mihal, Eric A. Sather | 2021-10-19 |
| 11152336 | 3D processor having stacked integrated circuit die | Ilyas Mohammed, Kenneth Duong, Javier A. Delacruz | 2021-10-19 |
| 11113603 | Training network with discrete weight values | Eric A. Sather | 2021-09-07 |
| 11049013 | Encoding of weight values stored on neural network inference circuit | Kenneth Duong, Jung Ko | 2021-06-29 |
| 11043006 | Use of machine-trained network for misalignment identification | Andrew C. Mihal | 2021-06-22 |
| 11017295 | Device storing ternary weight parameters for machine-trained network | Eric A. Sather | 2021-05-25 |
| 11003736 | Reduced dot product computation circuit | Kenneth Duong, Jung Ko | 2021-05-11 |
| 10978348 | 3D chip sharing power interconnect layer | Javier A. Delacruz, Ilyas Mohammed | 2021-04-13 |
| 10977338 | Reduced-area circuit for dot product computation | Kenneth Duong, Jung Ko | 2021-04-13 |
| 10970627 | Time borrowing between layers of a three dimensional chip stack | Kenneth Duong, Javier A. Delacruz | 2021-04-06 |
| 10950547 | Stacked IC structure with system level wiring on multiple sides of the IC die | Ilyas Mohammed, Javier A. Delacruz | 2021-03-16 |
| 10936951 | Machine learning through multiple layers of novel machine trained processing nodes | — | 2021-03-02 |
| 10892252 | Face-to-face mounted IC dies with orthogonal top interconnect layers | Eric Nequist, Javier A. Delacruz, Ilyas Mohammed, Laura Mirkarimi | 2021-01-12 |
| 10886177 | 3D chip with shared clock distribution network | Javier A. Delacruz, Ilyas Mohammed | 2021-01-05 |