Issued Patents 2021
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11195832 | High performance nanosheet fabrication method with enhanced high mobility channel elements | Mark I. Gardner | 2021-12-07 |
| 11177250 | Method for fabrication of high density logic and memory for advanced circuit architecture | Mark I. Gardner, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-11-16 |
| 11171208 | High performance circuit applications using stacked 3D metal lines | Mark I. Gardner, Anton J. deVilliers | 2021-11-09 |
| 11139213 | Method of making 3D source drains with hybrid stacking for optimum 3D logic layout | Mark I. Gardner | 2021-10-05 |
| 11133310 | Method of making multiple nano layer transistors to enhance a multiple stack CFET performance | Mark I. Gardner | 2021-09-28 |
| 11133206 | Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking | Anthony R. Schepis, Anton J. deVilliers | 2021-09-28 |
| 11114346 | High density logic formation using multi-dimensional laser annealing | Mark I. Gardner, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-09-07 |
| 11107733 | Multi-dimensional planes of logic and memory formation using single crystal silicon orientations | Mark I. Gardner, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-08-31 |
| 11069616 | Horizontal programmable conducting bridges between conductive lines | Mark I. Gardner, Anton J. deVilliers | 2021-07-20 |