Issued Patents 2020
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878165 | Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same | Chin-Chou Liu, Sheng-Hsiung Chen, Po-Hsiang Huang | 2020-12-29 |
| 10811316 | Method and system of forming integrated circuit | Ka Fai Chang, Chin-Chou Liu, Yi-Kan Cheng | 2020-10-20 |
| 10804200 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2020-10-13 |
| 10797041 | Integrated circuit, system for and method of forming an integrated circuit | Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan | 2020-10-06 |
| 10796060 | Method and system for pin layout | Li-Chun Tien, Shun Li Chen, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang | 2020-10-06 |
| 10776557 | Integrated circuit structure | Po-Hsiang Huang, Sheng-Hsiung Chen | 2020-09-15 |
| 10777505 | Method of fabricating integrated circuit having staggered conductive features | Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen | 2020-09-15 |
| 10741539 | Standard cells and variations thereof within a standard cell library | Sheng-Hsiung Chen, Jerry Chang Jui Kao, Po-Hsiang Huang, Shao-Huan Wang, XinYong WANG +2 more | 2020-08-11 |
| 10733352 | Integrated circuit and layout method for standard cell structures | Sheng-Hsiung Chen, Chung-Te Lin, Ho Che Yu, Li-Chun Tien | 2020-08-04 |
| 10678987 | Cell layout method and system for creating stacked 3D integrated circuit having two tiers | Sheng-Hsiung Chen | 2020-06-09 |
| 10665550 | Electromagnetic shielding metal-insulator-metal capacitor structure | Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Po-Hsiang Huang, Yi-Kan Cheng +1 more | 2020-05-26 |
| 10664565 | Method and system of expanding set of standard cells which comprise a library | Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang Jui Kao, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2020-05-26 |
| 10559558 | Pin modification for standard cells | Sheng-Hsiung Chen, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang, Lee-Chung Lu +2 more | 2020-02-11 |
| 10552568 | Method of modifying cell and global connection routing method | Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, I-Lun Tseng, Po-Hsiang Huang | 2020-02-04 |
| 10535635 | Second semiconductor wafer attached to a first semiconductor wafer with a through hole connected to an inductor | Chih-Lin Chen, Chin-Chou Liu, Hui Yu Lee, Po-Hsiang Huang | 2020-01-14 |