Issued Patents 2020
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10877897 | System, apparatus and method for multi-cacheline small object memory tagging | David M. Durham, Ron Gabor | 2020-12-29 |
| 10872011 | Internal error checking and correction (ECC) with extra system bits | Kuljit S. Bains, Bill Nale | 2020-12-22 |
| 10725861 | Error correction code memory security | Anatoli Bolotov, Mikhail I. Grinchuk | 2020-07-28 |
| 10719443 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman +5 more | 2020-07-21 |
| 10594491 | Cryptographic system memory management | David M. Durham, Siddhartha Chhabra, Sergej Deutsch, Karanvir S. Grewal, Ioannis T. Schoinas | 2020-03-17 |
| 10593019 | Method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded images | Anurag Mithalal Jain, Ravindranath Ramalingaiah Munnan, Venkata Ravisankar Jayanthi, Ashish Ranjan, Joy Dutta +5 more | 2020-03-17 |
| 10579464 | Method and apparatus for partial cache line sparing | Debaleena Das, Brian S. Morris | 2020-03-03 |