| 10872011 |
Internal error checking and correction (ECC) with extra system bits |
Kuljit S. Bains, Rajat Agarwal |
2020-12-22 |
| 10839887 |
Applying chip select for memory device identification and power management control |
Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth |
2020-11-17 |
| 10810141 |
Memory control management of a processor |
Mahesh S. Natu, Murugasamy K. Nachimuthu |
2020-10-20 |
| 10802532 |
Techniques to mirror a command/address or interpret command/address logic at a memory device |
George Vergis, Kuljit S. Bains |
2020-10-13 |
| 10795755 |
Method and apparatus for performing error handling operations using error signals |
Jonathan C. Jasper, Murugasamy K. Nachimuthu, Jun Zhu, Tuan M. Quach |
2020-10-06 |
| 10783028 |
Method and apparatus for setting high address bits in a memory module |
— |
2020-09-22 |
| 10747605 |
Method and apparatus for providing a host memory controller write credits for write commands |
Jun Zhu, Tuan M. Quach |
2020-08-18 |
| 10692560 |
Periodic calibrations during memory device self refresh |
Christopher E. Cox |
2020-06-23 |
| 10691626 |
Memory channel that supports near memory and far memory access |
Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi |
2020-06-23 |
| 10636476 |
Row hammer mitigation with randomization of target row selection |
— |
2020-04-28 |
| 10592445 |
Techniques to access or operate a dual in-line memory module via multiple data channels |
Christopher E. Cox, Kuljit S. Bains, George Vergis, James A. McCall, Chong J. Zhao +3 more |
2020-03-17 |
| 10579462 |
Method and apparatus for using an error signal to indicate a write request error and write request acceptance |
Jun Zhu, Tuan M. Quach |
2020-03-03 |