Issued Patents 2020
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10795823 | Dynamic partial power down of memory-side cache in a 2-level memory hierarchy | Raj K. Ramanujan, Glenn J. Hinton | 2020-10-06 |
| 10719443 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2020-07-21 |
| 10541009 | Write data mask for power reduction | Robert M. Ellis, Rajesh Sundaram | 2020-01-21 |