Issued Patents 2020
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10795595 | Technologies for lifecycle management with remote firmware | Murugasamy K. Nachimuthu | 2020-10-06 |
| 10791174 | Mechanism for efficient discovery of storage resources in a rack scale architecture system | Murugasamy K. Nachimuthu | 2020-09-29 |
| 10783048 | High performance persistent memory | Murugasamy K. Nachimuthu, George Vergis | 2020-09-22 |
| 10757487 | Accelerator resource allocation and pooling | Murugasamy K. Nachimuthu, Aaron Gorius, Michael T. Crocker | 2020-08-25 |
| 10756886 | Technologies for load balancing a network | Mrittika Ganguli, Yadong Li, Michael Orr, Anjaneya Reddy Chagam Reddy | 2020-08-25 |
| 10732986 | Computing platform with interface based error injection | Sarathy Jayakumar, Jose A. Vargas | 2020-08-04 |
| 10728024 | Technologies for providing runtime code in an option ROM | Murugasamy K. Nachimuthu | 2020-07-28 |
| 10719443 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2020-07-21 |
| 10687434 | Mechanisms for SAS-free cabling in rack scale design | Murugasamy K. Nachimuthu | 2020-06-16 |
| 10649690 | Fast memory initialization | George Vergis, Sarathy Jayakumar | 2020-05-12 |
| 10616669 | Dynamic memory for compute resources in a data center | Murugasamy K. Nachimuthu | 2020-04-07 |
| 10592162 | Distributed storage location hinting for non-volatile memories | Scott Peterson, Sujoy Sen, Anjaneya Reddy Chagam Reddy, Murugasamy K. Nachimuthu | 2020-03-17 |
| 10567166 | Technologies for dividing memory across socket partitions | Murugasamy K. Nachimuthu | 2020-02-18 |
| 10541942 | Technologies for accelerating edge device workloads | Francesc Guim Bernat, Anil Rao, Suraj Prabhakaran, Karthik Kumar | 2020-01-21 |