| 10877763 |
Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor |
Bryan Lloyd, Brian D. Barrick, Kurt A. Feiste, Dung Q. Nguyen, Kenneth L. Ward |
2020-12-29 |
| 10831537 |
Dynamic update of the number of architected registers assigned to software threads using spill counts |
Harold W. Cain, III, Hubertus Franke, Charles Ray Johns, Ravi Nair |
2020-11-10 |
| 10831501 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor |
Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto |
2020-11-10 |
| 10831498 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor |
Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto |
2020-11-10 |
| 10831481 |
Handling unaligned load operations in a multi-slice computer processor |
Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Jentje Leenstra, Dung Q. Nguyen +2 more |
2020-11-10 |
| 10761856 |
Instruction completion table containing entries that share instruction tags |
Kenneth L. Ward, Dung Q. Nguyen, Susan E. Eisen |
2020-09-01 |
| 10747545 |
Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor |
Michael J. Genden, Dung Q. Nguyen, Brian W. Thompto |
2020-08-18 |
| 10691459 |
Converting multiple instructions into a single combined instruction with an extension opcode |
Giles R. Frazier, Jose E. Moreira, Brian W. Thompto |
2020-06-23 |
| 10684856 |
Converting multiple instructions into a single combined instruction with an extension opcode |
Giles R. Frazier, Jose E. Moreira, Brian W. Thompto |
2020-06-16 |
| 10664275 |
Speeding up younger store instruction execution after a sync instruction |
Susan E. Eisen, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more |
2020-05-26 |
| 10635444 |
Shared compare lanes for dependency wake up in a pair-based issue queue |
Michael J. Genden, Dung Q. Nguyen, Brian W. Thomto |
2020-04-28 |
| 10564978 |
Operation of a multi-slice processor with an expanded merge fetching queue |
Kimberly M. Fernsler, David A. Hrusecky, Elizabeth A. McGlone, Brian W. Thompto |
2020-02-18 |
| 10545762 |
Independent mapping of threads |
Sam Gat-Shang Chu, Markus Kaltenbach, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more |
2020-01-28 |
| 10545765 |
Multi-level history buffer for transaction memory in a microprocessor |
Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Dung Q. Nguyen, David R. Terry +1 more |
2020-01-28 |
