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Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor |
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| 10831489 |
Mechanism for completing atomic instructions in a microprocessor |
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| 10831492 |
Most favored branch issue |
Salma Ayub, Glenn O. Kincaid, Christopher M. Mueller, Dung Q. Nguyen, Eula Faye Abalos Tolentino +1 more |
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| 10761856 |
Instruction completion table containing entries that share instruction tags |
Dung Q. Nguyen, Hung Q. Le, Susan E. Eisen |
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| 10725786 |
Completion mechanism for a microprocessor instruction completion table |
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| 10713057 |
Mechanism to stop completions using stop codes in an instruction completion table |
Dung Q. Nguyen, Susan E. Eisen, Christopher M. Mueller, Joe Lee, Deepak Singh |
2020-07-14 |
| 10552165 |
Efficiently managing speculative finish tracking and error handling for load instructions |
Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr. |
2020-02-04 |
