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Mechanism for completing atomic instructions in a microprocessor |
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2020-11-10 |
| 10761856 |
Instruction completion table containing entries that share instruction tags |
Kenneth L. Ward, Dung Q. Nguyen, Hung Q. Le |
2020-09-01 |
| 10740140 |
Flush-recovery bandwidth in a processor |
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| 10725786 |
Completion mechanism for a microprocessor instruction completion table |
Kenneth L. Ward, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh |
2020-07-28 |
| 10713057 |
Mechanism to stop completions using stop codes in an instruction completion table |
Kenneth L. Ward, Dung Q. Nguyen, Christopher M. Mueller, Joe Lee, Deepak Singh |
2020-07-14 |
| 10664275 |
Speeding up younger store instruction execution after a sync instruction |
Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more |
2020-05-26 |
| 10552165 |
Efficiently managing speculative finish tracking and error handling for load instructions |
David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward |
2020-02-04 |
| 10528347 |
Executing system call vectored instructions in a multi-slice processor |
Nicholas R. Orzol, Mehul Patel, Eula A. Tolentino |
2020-01-07 |