| 10831501 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor |
Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2020-11-10 |
| 10831498 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor |
Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2020-11-10 |
| 10776122 |
Prioritization protocols of conditional branch instructions |
Eula Faye Abalos Tolentino, Dung Q. Nguyen, Jeffrey C. Brownscheidle, Tu-An T. Nguyen, David S. Walder |
2020-09-15 |
| 10747545 |
Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor |
Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2020-08-18 |
| 10740104 |
Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch |
Jentje Leenstra, Nicholas R. Orzol, Christian Zoellin, Robert Alan Philhower |
2020-08-11 |
| 10719056 |
Merging status and control data in a reservation station |
Brian D. Barrick, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Dhivya Jeganathan +2 more |
2020-07-21 |
| 10678547 |
Low latency execution of floating-point record form instructions |
Brian J. D. Barrick, Maarten J. Boersma, Niels Fricke |
2020-06-09 |
| 10671399 |
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core |
Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael K. Kroener, David R. Terry |
2020-06-02 |
| 10671398 |
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core |
Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael K. Kroener, David R. Terry |
2020-06-02 |
| 10635444 |
Shared compare lanes for dependency wake up in a pair-based issue queue |
Dung Q. Nguyen, Hung Q. Le, Brian W. Thomto |
2020-04-28 |
| 10592246 |
Low latency execution of floating-point record form instructions |
Brian J. D. Barrick, Maarten J. Boersma, Niels Fricke |
2020-03-17 |
