Issued Patents 2020
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831661 | Coherent cache with simultaneous data requests in same addressable index | Tim Bronson, Robert J. Sonnelitter, III, Deanna Postles Dunn Berger, Chad G. Wilson, Kenneth D. Klapproth +3 more | 2020-11-10 |
| 10824565 | Configuration based cache coherency protocol selection | Deanna Postles Dunn Berger, Michael Fee, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2020-11-03 |
| 10649908 | Non-disruptive clearing of varying address ranges from cache | Deanna Postles Dunn Berger, Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy +1 more | 2020-05-12 |
| 10528253 | Increased bandwidth of ordered stores in a non-uniform memory subsystem | Garrett M. Drapala, Norbert Hagspiel, Sascha Junghans, Matthias Klein, Gary E. Strait | 2020-01-07 |
| 10529396 | Preinstall of partial store cache lines | Sascha Junghans, Matthias Klein, Pak-kin Mak, Robert J. Sonnelitter, III, Chad G. Wilson | 2020-01-07 |