Issued Patents 2019
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515822 | Method for preventing bottom layer wrinkling in a semiconductor device | Jung-Hau Shiu, Tze-Liang Lee, Yu-Yun Peng | 2019-12-24 |
| 10516036 | Spacer structure with high plasma resistance for semiconductor devices | Wan-Yi Kao | 2019-12-24 |
| 10516035 | Semiconductor device structure with a low-k spacer layer and method for manufacturing the same | Hsiang-Wei Lin | 2019-12-24 |
| 10510584 | Via patterning using multiple photo multiple etch | Jung-Hau Shiu, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng | 2019-12-17 |
| 10510585 | Multi-patterning to form vias with straight profiles | Chun-Kai Chen, Jung-Hau Shiu, Chia-Cheng Chou, Tze-Liang Lee, Chih-Hao Chen +1 more | 2019-12-17 |
| 10510852 | Low-k feature formation processes and structures formed thereby | Wan-Yi Kao | 2019-12-17 |
| 10483372 | Spacer structure with high plasma resistance for semiconductor devices | Wan-Yi Kao | 2019-11-19 |
| 10340178 | Via patterning using multiple photo multiple etch | Jung-Hau Shiu, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng | 2019-07-02 |
| 10332836 | Methods for reducing dual damascene distortion | Chao-Chun Wang, Po-Cheng Shih | 2019-06-25 |
| 10312107 | Forming interconnect structure using plasma treated metal hard mask | Chia-Cheng Chou, Shing-Chyang Pan, Keng-Chu Lin, Shwang-Ming Jeng | 2019-06-04 |
| 10304677 | Low-k feature formation processes and structures formed thereby | Wan-Yi Kao, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin +2 more | 2019-05-28 |
| 10269627 | Interconnect structure and method | Chia-Cheng Chou, Chih-Chien Chi, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo +3 more | 2019-04-23 |