Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522489 | Manufacturing process for separating logic and memory array | Hem Takiar, Michael Mostovoy, Emilio Yero, Yan Li | 2019-12-31 |
| 10483239 | Semiconductor device including dual pad wire bond interconnection | Junrong Yan, Xiaofeng Di, Harjashan Veer Singh, Chee Keong Chin, Ming Xia Wu +1 more | 2019-11-19 |
| 10468073 | Transmission line optimization for multi-die systems | John Contreras | 2019-11-05 |
| 10381327 | Non-volatile memory system with wide I/O memory die | Venkatesh Ramachandra, Michael Mostovoy, Hem Takiar, Vinayak Ghatawade | 2019-08-13 |
| 10249592 | Wire bonded wide I/O semiconductor device | Michael Mostovoy, Ning Ye, Hem Takiar, Venkatesh Ramachandra, Vinayak Ghatawade +1 more | 2019-04-02 |