Issued Patents 2019
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10423412 | Instructions to count contiguous register elements having a specific value in a selected location | Michael K. Gschwind, Jentje Leenstra, Brett Olsson | 2019-09-24 |
| 10417127 | Selective downstream cache processing for data access | Willm Hinrichs, Eyal Naor, Martin Recktenwald | 2019-09-17 |
| 10409724 | Selective downstream cache processing for data access | Willm Hinrichs, Eyal Naor, Martin Recktenwald | 2019-09-10 |
| 10387150 | Instructions to count contiguous register elements having a specific value in a selected location | Michael K. Gschwind, Jentje Leenstra, Brett Olsson | 2019-08-20 |
| 10380033 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2019-08-13 |
| 10380032 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2019-08-13 |
| 10380034 | Cache return order optimization | Ulrich Mayer, Siegmund Schlechter, Maxim Scholl | 2019-08-13 |
| 10317465 | Integrated circuit chip and a method for testing the same | Wilhelm Haller, Ulrich Krauch, Nicolas Maeding, Christian Zoellin | 2019-06-11 |
| 10268582 | Operating different processor cache levels | Simon H. Friedmann, Christian Jacobi, Ulrich Mayer, Anthony Saporito | 2019-04-23 |
| 10229061 | Method and arrangement for saving cache power | Christian Jacobi, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2019-03-12 |
| 10169234 | Translation lookaside buffer purging with concurrent cache updates | Simon H. Friedmann, Dietmar Schmunkamp, Johannes C. Reichart | 2019-01-01 |
| 10169233 | Translation lookaside buffer purging with concurrent cache updates | Simon H. Friedmann, Dietmar Schmunkamp, Johannes C. Reichart | 2019-01-01 |