MI

Mahesh A. Iyer

IN Intel: 15 patents #101 of 5,769Top 2%
SY Synopsys: 1 patents #61 of 330Top 20%
Overall (2019): #3,223 of 560,194Top 1%
16
Patents 2019

Issued Patents 2019

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
10523224 Techniques for signal skew compensation David W. Mendel, Carl Ebeling, Dana How 2019-12-31
10489535 Method and apparatus for reducing constraints during rewind structural verification of retimed circuits Vasudeva M. Kamath 2019-11-26
10417374 Method and apparatus for performing register retiming by utilizing native timing-driven constraints 2019-09-17
10394993 Discretizing gate sizes during numerical synthesis Amir H. Mottaez 2019-08-27
10372850 Methods for verifying retimed circuits with delayed initialization 2019-08-06
10354038 Methods for bounding the number of delayed reset clock cycles for retimed circuits 2019-07-16
10339241 Methods for incremental circuit design legalization during physical synthesis Robert Walker 2019-07-02
10333535 Techniques for signal skew compensation David W. Mendel, Carl Ebeling, Dana How 2019-06-25
10318686 Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph Shounak Dhar, Love Singhal, Nikolay Rubanov, Saurabh Adya 2019-06-11
10303202 Method and apparatus for performing clock allocation for a system implemented on a programmable device Saurabh Adya, Love Singhal 2019-05-28
10296701 Retiming with fixed power-up states Vasudeva M. Kamath, Robert Walker 2019-05-21
10255404 Retiming with programmable power-up states Vasudeva M. Kamath, Robert Walker 2019-04-09
10242144 Methods for minimizing logic overlap on integrated circuits Saurabh Adya, Love Singhal 2019-03-26
10235485 Partial reconfiguration debugging using hybrid models Kalen B. Brunham 2019-03-19
10181001 Methods and apparatus for automatically implementing a compensating reset for retimed circuitry Sean R. Atsatt 2019-01-15
10169518 Methods for delaying register reset for retimed circuits 2019-01-01