Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10318686 | Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph | Shounak Dhar, Mahesh A. Iyer, Love Singhal, Nikolay Rubanov | 2019-06-11 |
| 10303202 | Method and apparatus for performing clock allocation for a system implemented on a programmable device | Mahesh A. Iyer, Love Singhal | 2019-05-28 |
| 10242144 | Methods for minimizing logic overlap on integrated circuits | Mahesh A. Iyer, Love Singhal | 2019-03-26 |