Issued Patents 2019
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10318686 | Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph | Shounak Dhar, Mahesh A. Iyer, Love Singhal, Saurabh Adya | 2019-06-11 |