Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10073135 | Alignment testing for tiered semiconductor structure | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee | 2018-09-11 |
| 10067181 | Testing holders for chip unit and die package | Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2018-09-04 |
| 10002829 | Semiconductor device and manufacturing method thereof | Hao Chen, Chen-Hsiang Hsu, Hung-Chih Lin, Ching-Nen Peng | 2018-06-19 |
| 9952279 | Apparatus for three dimensional integrated circuit testing | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang, Chung-Sheng Yuan +3 more | 2018-04-24 |
| 9915699 | Integrated fan-out pillar probe system | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee, Chen-Hung Tien +1 more | 2018-03-13 |
| 9900970 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2018-02-20 |
| 9891266 | Test circuit and method | Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen | 2018-02-13 |
| 9880201 | Systems for probing semiconductor wafers | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2018-01-30 |
| 9859176 | Semiconductor device, test system and method of the same | Tang-Jung Chiu, Hung-Chih Lin, Hao Chen | 2018-01-02 |