Issued Patents 2018
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10153038 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen, Sahil Preet Singh | 2018-12-11 |
| 10008253 | Array architecture and write operations of thyristor based random access memory | Yue-Der Chih, Carlos H. Diaz, Jean-Pierre Colinge | 2018-06-26 |
| 9997219 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Yen-Huei Chen +2 more | 2018-06-12 |
| 9959916 | Dual rail memory, memory macro and associated hybrid power supply method | Chiting Cheng, Cheng Hung Lee, Hung-Jen Liao, Michael Patrick Clinton | 2018-05-01 |
| 9922700 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen, Sahil Preet Singh | 2018-03-20 |
| 9865605 | Memory circuit having resistive device coupled with supply voltage line | Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Wei-Cheng Wu | 2018-01-09 |