Issued Patents 2018
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157666 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying | 2018-12-18 |
| 10153038 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2018-12-11 |
| 10134737 | Memory device with reduced-resistance interconnect | Yen-Huei Chen | 2018-11-20 |
| 10127951 | Memory device with reduced-resistance interconnect | — | 2018-11-13 |
| 10037796 | Generating a collapsed VDD using a write-assist column to decrease a write voltage | Yen-Huei Chen | 2018-07-31 |
| 9928899 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying | 2018-03-27 |
| 9922700 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2018-03-20 |
| 9911473 | Circuit with self-adjust pre-charged global data line | Li-Wen Wang, Manish Arora | 2018-03-06 |