Issued Patents 2018
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163491 | Memory circuit having shared word line | Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen | 2018-12-25 |
| 10153038 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2018-12-11 |
| 10083739 | Three-dimensional three-port bit cell and method of assembling same | Tzu-Kuei Lin, Yen-Huei Chen, Ching-Wei Wu | 2018-09-25 |
| 10062419 | Digtial circuit structures | Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen | 2018-08-28 |
| 10024906 | Timing skew characterization apparatus and method | Chao Kai Chuang, Yen-Chien Lai | 2018-07-17 |
| 9997219 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Jonathan Tsung-Yung Chang, Yen-Huei Chen +2 more | 2018-06-12 |
| 9979399 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hau-Tai Shieh, Che-Ju Yeh | 2018-05-22 |
| 9959916 | Dual rail memory, memory macro and associated hybrid power supply method | Jonathan Tsung-Yung Chang, Chiting Cheng, Cheng Hung Lee, Michael Patrick Clinton | 2018-05-01 |
| 9922701 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Chiting Cheng, Tsung-Yung Chang | 2018-03-20 |
| 9922700 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2018-03-20 |
| 9886996 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2018-02-06 |
| 9865605 | Memory circuit having resistive device coupled with supply voltage line | Yen-Huei Chen, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2018-01-09 |