Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163723 | Self-aligned nanowire formation using double patterning | Ching-Feng Fu, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin | 2018-12-25 |
| 10032639 | Methods for improved critical dimension uniformity in a semiconductor device fabrication process | Chi-Cheng Hung, Chun-Kuang Chen, Wei-Liang Lin, Yu-Tien Shen | 2018-07-24 |
| 10026658 | Methods for fabricating vertical-gate-all-around transistor structures | Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Huan-Just Lin | 2018-07-17 |
| 9991132 | Lithographic technique incorporating varied pattern materials | Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, Ru-Gun Liu, Tsai-Sheng Gau +1 more | 2018-06-05 |
| 9966448 | Method of making a silicide beneath a vertical structure | Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, Huang-Yi Huang, Hui-Cheng Chang +2 more | 2018-05-08 |
| 9954069 | Semiconductor device and method of forming vertical structure | Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang +4 more | 2018-04-24 |
| 9941394 | Tunnel field-effect transistor | Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chih-Tang Peng, Hung-Ta Lin +1 more | 2018-04-10 |
| 9934971 | Method of forming an integrated circuit using a patterned mask layer | Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, Chao-Cheng Chen | 2018-04-03 |
| 9911661 | Nano wire structure and method for fabricating the same | Ching-Feng Fu, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin | 2018-03-06 |