Issued Patents 2018
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157254 | Techniques based on electromigration characteristics of cell interconnect | Kuo-Nan Yang, Yi-Kan Cheng, Kumar Lalgudi | 2018-12-18 |
| 10157840 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2018-12-18 |
| 10157258 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang | 2018-12-18 |
| 10157257 | Method for analyzing an electromigration (EM) rule violation in an integrated circuit | Wan-Yu Lo, Chin-Shen Lin, Kuo-Nan Yang | 2018-12-18 |
| 10074641 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2018-09-11 |
| 10055531 | Layout checking method for advanced double patterning photolithography with multiple spacing criteria | King-Ho Tam, Yuan-Te Hou, Chin-Chang Hsu, Meng-Kai Hsu | 2018-08-21 |
| 10050028 | Semiconductor device with reduced leakage current | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Yi-Hsun Chiu +1 more | 2018-08-14 |
| 9984192 | Cell having shifted boundary and boundary-shift scheme | Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao | 2018-05-29 |
| 9953122 | Integrated circuit design method and associated non-transitory computer-readable medium | Yu-Jen Chang, Kuo-Nan Yang, Jui-Jung Hsu, Chih-Hung Wu | 2018-04-24 |
| 9893009 | Duplicate layering and routing | Huang-Yu Chen, Chi-Yeh Yu | 2018-02-13 |