Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163880 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2018-12-25 |
| 10157840 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Po-Hsiang Huang +6 more | 2018-12-18 |
| 10157910 | Circuits and structures including tap cells and fabrication methods thereof | Jin Xu, Ting-Wei Chiang, Hui-Zhong Zhuang | 2018-12-18 |
| 10157902 | Semiconductor devices with cells comprising routing resources | Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Chi-Yu Lu | 2018-12-18 |
| 10141256 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2018-11-27 |
| 10127340 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Chi-Yu Lu | 2018-11-13 |
| 10007750 | Gate pad layout patterns for masks and structures | Ting-Wei Chiang, Shun Li Chen, Yi-Hsun Chiu | 2018-06-26 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang +1 more | 2018-06-05 |
| 9899263 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang +1 more | 2018-02-20 |