Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163883 | Layout method for integrated circuit and layout of the integrated circuit | Cheok-Kei Lei, Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu +3 more | 2018-12-25 |
| 10163880 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Pin-Dai Sue, Li-Chun Tien | 2018-12-25 |
| 10157902 | Semiconductor devices with cells comprising routing resources | Mao-Wei Chiu, Ting-Wei Chiang, Li-Chun Tien, Chi-Yu Lu | 2018-12-18 |
| 10157910 | Circuits and structures including tap cells and fabrication methods thereof | Jin Xu, Ting-Wei Chiang, Li-Chun Tien | 2018-12-18 |
| 10141256 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Li-Chun Tien, Pin-Dai Sue | 2018-11-27 |
| 10127340 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Mao-Wei Chiu, Ting-Wei Chiang, Li-Chun Tien, Chi-Yu Lu | 2018-11-13 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien +1 more | 2018-06-05 |
| 9984191 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu +2 more | 2018-05-29 |
| 9899263 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Min-Hsiung Chiang, Ting-Wei Chiang +1 more | 2018-02-20 |