Issued Patents 2018
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163882 | Semiconductor device and layout thereof | Cheng-I Huang, Shih-Chi Fu, Sheng-Fang Cheng, Jung-Chan Yang | 2018-12-25 |
| 10163880 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien | 2018-12-25 |
| 10157902 | Semiconductor devices with cells comprising routing resources | Mao-Wei Chiu, Hui-Zhong Zhuang, Li-Chun Tien, Chi-Yu Lu | 2018-12-18 |
| 10157910 | Circuits and structures including tap cells and fabrication methods thereof | Jin Xu, Hui-Zhong Zhuang, Li-Chun Tien | 2018-12-18 |
| 10141256 | Semiconductor device and layout design thereof | Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue | 2018-11-27 |
| 10127340 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Mao-Wei Chiu, Hui-Zhong Zhuang, Li-Chun Tien, Chi-Yu Lu | 2018-11-13 |
| 10007750 | Gate pad layout patterns for masks and structures | Shun Li Chen, Yi-Hsun Chiu, Li-Chun Tien | 2018-06-26 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien +1 more | 2018-06-05 |
| 9899263 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang +1 more | 2018-02-20 |
| 9882002 | FinFET with an asymmetric source/drain structure and method of making same | Hsiang-Jen Tseng, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo | 2018-01-30 |