Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10090244 | Standard cell circuits employing high aspect ratio voltage rails for reduced resistance | Jeffrey Junhao Xu, Mustafa Badaroglu, Periannan Chidambaram | 2018-10-02 |
| 10079293 | Semiconductor device having a gap defined therein | Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu +2 more | 2018-09-18 |
| 10043796 | Vertically stacked nanowire field effect transistors | Vladimir Machkaoutsan, Stanley Seungchul Song, Mustafa Badaroglu, John Jianhong Zhu, Junjing Bao +3 more | 2018-08-07 |
| 10032678 | Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices | Jeffrey Junhao Xu, Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Choh Fei Yeap | 2018-07-24 |
| 9997360 | Method for mitigating layout effect in FINFET | Yanxiang Liu, Jun Yuan, Kern Rim | 2018-06-12 |
| 9985014 | Minimum track standard cell circuits for reduced area | Jeffrey Junhao Xu, Mustafa Badaroglu | 2018-05-29 |
| 9953979 | Contact wrap around structure | Jeffrey Junhao Xu, Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Junjing Bao +2 more | 2018-04-24 |
| 9871121 | Semiconductor device having a gap defined therein | Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu +2 more | 2018-01-16 |
| 9859210 | Integrated circuits having reduced dimensions between components | Stanley Seungchul Song, Choh Fei Yeap | 2018-01-02 |