Issued Patents 2018
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157794 | Integrated circuit structure with stepped epitaxial region | Puneet Harischandra Suvarna, Mark V. Raymond, Peter M. Zeitzoff | 2018-12-18 |
| 10141446 | Formation of bottom junction in vertical FET devices | Hiroaki Niimi, Kwan-Yong Lim, Daniel Chanemougame | 2018-11-27 |
| 10141414 | Negative capacitance matching in gate electrode structures | Rohit Galatage, Puneet Harischandra Suvarna, Zoran Krivokapic | 2018-11-27 |
| 10056377 | Metal layer routing level for vertical FET SRAM and logic cell scaling | Bipul C. Paul | 2018-08-21 |
| 9991352 | Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device | Julien Frougier, Ali Razavieh, Ruilong Xie | 2018-06-05 |
| 9972494 | Method and structure to control channel length in vertical FET device | Ruilong Xie | 2018-05-15 |
| 9966456 | Methods of forming gate electrodes on a vertical transistor device | Chanro Park, Hoon Kim, Min Gyu Sung, Ruilong Xie | 2018-05-08 |
| 9960086 | Methods, apparatus and system for self-aligned retrograde well doping for finFET devices | Mira Park, Kwan-Yong Lim, Amitabh Jain | 2018-05-01 |
| 9947804 | Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure | Julien Frougier, Min Gyu Sung, Ruilong Xie, Chanro Park | 2018-04-17 |
| 9865682 | Directed self-assembly material etch mask for forming vertical nanowires | Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob | 2018-01-09 |