Issued Patents 2018
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157131 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-12-18 |
| 10120803 | Transactional memory coherence control | Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-11-06 |
| 10120802 | Transactional memory coherence control | Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-11-06 |
| 10055348 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-08-21 |
| 10019357 | Supporting atomic accumulation with an addressable accumulator | Michael K. Gschwind, Eric M. Schwarz | 2018-07-10 |
| 10013351 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-07-03 |
| 9983904 | Multithreaded transactions | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-05-29 |
| 9971601 | Dynamic assignment across dispatch pipes of source ports to be used to obtain indication of physical registers | Gregory W. Alexander, Brian D. Barrick, Wen H. Li, Edward T. Malley | 2018-05-15 |
| 9971626 | Coherence protocol augmentation to indicate transaction status | Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura, Eric M. Schwarz +1 more | 2018-05-15 |
| 9940135 | Instruction stream modification for memory transaction protection | Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura, Timothy J. Slegel | 2018-04-10 |
| 9928132 | Dynamic accessing of execution elements through modification of issue rules | Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum | 2018-03-27 |
| 9928064 | Instruction stream modification for memory transaction protection | Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura, Timothy J. Slegel | 2018-03-27 |
| 9921834 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-03-20 |
| 9921849 | Address expansion and contraction in a multithreading computer system | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-03-20 |
| 9921848 | Address expansion and contraction in a multithreading computer system | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-03-20 |
| 9904572 | Dynamic prediction of hardware transaction resource requirements | Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2018-02-27 |
| 9898290 | Efficiency for coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-02-20 |
| 9898289 | Coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2018-02-20 |
| 9875107 | Accelerated execution of execute instruction target | Khary J. Alexander, Brian W. Curran, David S. Hutton, Edward T. Malley, Brian R. Prasky +1 more | 2018-01-23 |
| 9870254 | Multithreaded transactions | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-01-16 |
| 9864639 | Management of resources within a computing environment | Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum | 2018-01-09 |