Issued Patents 2018
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157119 | Configurable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Chung-Lung K. Shum | 2018-12-18 |
| 10120681 | Compare and delay instructions | Charles W. Gainey, Jr., Dan F. Greiner, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2018-11-06 |
| 10083124 | Translating virtual memory addresses to physical addresses | Uwe Brandt, Markus Helms, Markus Kaltenbach, Thomas Koehler, Frank Lehnert | 2018-09-25 |
| 10068069 | Denoting precise locations and arguments in binary program code | — | 2018-09-04 |
| 10025589 | Conditional transaction end instruction | Dan F. Greiner, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2018-07-17 |
| 9996360 | Transaction abort instruction specifying a reason for abort | Dan F. Greiner, Marcel Mitran, Timothy J. Slegel | 2018-06-12 |
| 9983881 | Selectively controlling instruction execution in transactional processing | Dan F. Greiner, Robert R. Rogers, Timothy J. Slegel | 2018-05-29 |
| 9983915 | Facilitating transaction completion subsequent to repeated aborts of the transaction | Brenton F. Belmar, Randall W. Philley, Timothy J. Slegel | 2018-05-29 |
| 9983883 | Transaction abort instruction specifying a reason for abort | Dan F. Greiner, Marcel Mitran, Timothy J. Slegel | 2018-05-29 |
| 9983882 | Selectively controlling instruction execution in transactional processing | Dan F. Greiner, Robert R. Rogers, Timothy J. Slegel | 2018-05-29 |
| 9971626 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2018-05-15 |
| 9959117 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9959118 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-05-01 |
| 9952862 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwartz, Timothy J. Slegel | 2018-04-24 |
| 9946589 | Structure for reducing power consumption for memory device | Gregory W. Alexander, Khary J. Alexander, Ilya Granovsky, Gregory Miaskovsky, James R. Mitchell | 2018-04-17 |
| 9946588 | Structure for reducing power consumption for memory device | Gregory W. Alexander, Khary J. Alexander, Ilya Granovsky, Gregory Miaskovsky, James R. Mitchell | 2018-04-17 |
| 9946542 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-04-17 |
| 9946521 | Programmable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Chung-Lung K. Shum | 2018-04-17 |
| 9940264 | Load and store ordering for a strongly ordered simultaneous multithreading core | Khary J. Alexander, Jonathan T. Hsieh, Martin Recktenwald | 2018-04-10 |
| 9910769 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2018-03-06 |
| 9904618 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2018-02-27 |
| 9898348 | Resource mapping in multi-threaded central processor units | Khary J. Alexander, Markus Helms, Bernd Nerz, Volker Urban | 2018-02-20 |
| 9886327 | Resource mapping in multi-threaded central processor units | Khary J. Alexander, Markus Helms, Bernd Nerz, Volker Urban | 2018-02-06 |
| 9886397 | Load and store ordering for a strongly ordered simultaneous multithreading core | Khary J. Alexander, Jonathan T. Hsieh, Martin Recktenwald | 2018-02-06 |
| 9858082 | Restricted instructions in transactional execution | Dan F. Greiner, Timothy J. Slegel | 2018-01-02 |