Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768186 | Three dimensional memory device having well contact pillar and method of making thereof | Ryoichi Honma, Hiroyuki Ogawa, Yuki Mizutani, Fumiaki Toyama | 2017-09-19 |
| 9728499 | Set of stepped surfaces formation for a multilevel interconnect structure | Hiroaki Iuchi, Michiaki Sano, Naoki Takeguchi | 2017-08-08 |
| 9711650 | Vertical thin film transistor selection devices and methods of fabrication | — | 2017-07-18 |
| 9608043 | Method of operating memory array having divided apart bit lines and partially divided bit line selector switches | Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi | 2017-03-28 |
| 9589839 | Method of reducing control gate electrode curvature in three-dimensional memory devices | Yusuke Ikawa, Kiyohiko Sakakibara, Eisuke Takii, Kengo Kajiwara, Akira Matsudaira +1 more | 2017-03-07 |
| 9576967 | Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings | Hajime Kimura, Shuji Minagawa, Michiaki Sano, Masanori Tsutsumi | 2017-02-21 |