Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818801 | Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof | Peter Rabkin, Perumal Ratnam, Christopher J. Petti | 2017-11-14 |
| 9780108 | Ultrathin semiconductor channel three-dimensional memory devices | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2017-10-03 |
| 9761604 | 3D vertical NAND with III-V channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2017-09-12 |
| 9721963 | Three-dimensional memory device having a transition metal dichalcogenide channel | Peter Rabkin | 2017-08-01 |
| 9711229 | 3D NAND with partial block erase | Peter Rabkin | 2017-07-18 |
| 9685484 | Reversible resistivity memory with crystalline silicon bit line | Peter Rabkin, Perumal Ratnam, Chris Petti | 2017-06-20 |
| 9685454 | Method of forming 3D vertical NAND with III-V channel | Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier | 2017-06-20 |
| 9634097 | 3D NAND with oxide semiconductor channel | Peter Rabkin, Johann Alsmeier | 2017-04-25 |
| 9613975 | Bridge line structure for bit line connection in a three-dimensional semiconductor device | Chenche Huang, Chun-Ming Wang, Yuki Mizutani, Hiroaki Koketsu, Masayuki Hiroi | 2017-04-04 |
| 9563504 | Partial block erase for data refreshing and open-block programming | Guirong Liang, Zhenming Zhou | 2017-02-07 |
| 9564226 | Smart verify for programming non-volatile memory | Mohan Dunga, Gerrit Jan Hemink, Zhenming Zhou | 2017-02-07 |