Issued Patents 2017
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852783 | Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages | Taehui Na, Byung Kyu Song, Seong-Ook Jung, Seung H. Kang | 2017-12-26 |
| 9812222 | Method and apparatus for in-system management and repair of semi-conductor memory failure | Dexter Tamio Chun, Jungwon Suh, Deepti Vijayalakshmi Sriramagiri, Yanru Li, Mosaddiq Saifuddin +1 more | 2017-11-07 |
| 9800271 | Error correction and decoding | Seong-Ook Jung, Sara Choi, Byung Kyu Song, Taehui Na, Jisu Kim +3 more | 2017-10-24 |
| 9799824 | STT-MRAM design enhanced by switching current induced magnetic field | William Xia, Wenqing Wu, Kendrick Hoy Leong Yuen, Abhishek Banerjee, Xia Li +1 more | 2017-10-24 |
| 9753874 | Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems | Adam E. Newham, Rashid Ahmed Akbar Attar, Seung H. Kang, Sungryul Kim, Taehyun Kim | 2017-09-05 |
| 9728259 | Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin | Seong-Ook Jung, Byung Kyu Song, Taehui Na, Seung H. Kang | 2017-08-08 |
| 9704557 | Method and apparatus for storing retention time profile information based on retention time and temperature | Xiangyu Dong, Deepti Vijayalakshmi Sriramagiri, Jungwon Suh | 2017-07-11 |
| 9691462 | Latch offset cancelation for magnetoresistive random access memory | Seong-Ook Jung, Taehui Na, Byungkyu Song, Seung H. Kang | 2017-06-27 |
| 9679663 | OTP cell with reversed MTJ connection | Taehyun Kim, Kangho Lee, Seung H. Kang, Xia Li, Wah Nam Hsu | 2017-06-13 |
| 9672885 | MRAM word line power control scheme | Sungryul Kim, Taehyun Kim, Seung H. Kang, Matthew Michael Nowak, Manoj Bhatnagar | 2017-06-06 |
| 9666274 | System and method for MRAM having controlled averagable and isolatable voltage reference | Taehyun Kim | 2017-05-30 |
| 9666259 | Dual mode sensing scheme | Seong-Ook Jung, Taehui Na, Byung Kyu Song, Seung H. Kang | 2017-05-30 |
| 9653183 | Shared built-in self-analysis of memory systems employing a memory array tile architecture | Hyunsuk Shin, Sungryul Kim | 2017-05-16 |
| 9633706 | Voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation | Sungryul Kim, Hyunsuk Shin | 2017-04-25 |
| 9612908 | Performing memory data scrubbing operations in processor-based memory in response to periodic memory controller wake-up periods | Taehyun Kim, Sungryul Kim | 2017-04-04 |
| 9583170 | Adjusting resistive memory write driver strength based on a mimic resistive memory write operation | Taehyun Kim, Sungryul Kim | 2017-02-28 |
| 9583219 | Method and apparatus for in-system repair of memory in burst refresh | Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri, Jungwon Suh | 2017-02-28 |
| 9583171 | Write driver circuits for resistive random access memory (RAM) arrays | Sungryul Kim, Taehyun Kim | 2017-02-28 |
| 9552244 | Real time correction of bit failure in resistive memory | Taehyun Kim, Sungryul Kim | 2017-01-24 |