Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831098 | Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing | Xinyuan Dou, Satyajit Shinde, Sandeep Gaan, Tao Han, Carlos M. Chacon +1 more | 2017-11-28 |
| 9786607 | Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer | Su Chen Fan, William J. Taylor, Jr. | 2017-10-10 |
| 9728456 | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | Su Chen Fan, William J. Taylor, Jr. | 2017-08-08 |
| 9722053 | Methods, apparatus and system for local isolation formation for finFET devices | Min Gyu Sung, Ruilong Xie, Hoon Kim, Chanro Park | 2017-08-01 |
| 9646884 | Block level patterning process | Chanro Park, Hoon Kim, Min Gyu Sung | 2017-05-09 |
| 9583442 | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | Su Chen Fan, William J. Taylor, Jr. | 2017-02-28 |