Issued Patents 2017
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852803 | Dummy word line control scheme for non-volatile memory | Vinh Diep, Liang Pang, Yingda Dong | 2017-12-26 |
| 9830963 | Word line-dependent and temperature-dependent erase depth | Liang Pang, Vinh Diep, Yingda Dong | 2017-11-28 |
| 9831118 | Reducing neighboring word line in interference using low-k oxide | Liang Pang, Yingda Dong, Jayavel Pachamuthu | 2017-11-28 |
| 9831114 | Self-aligned trench isolation in integrated circuits | Lei Xue, Kenichi Ohtsuka, Rinji Sugino, Simon S. Chan | 2017-11-28 |
| 9779948 | Method of fabricating 3D NAND | Ashish Baraskar, Yanli Zhang, Zhenyu Lu | 2017-10-03 |
| 9761320 | Reducing hot electron injection type of read disturb during read recovery phase in 3D memory | Hong-Yan Chen, Wei Zhao | 2017-09-12 |
| 9748266 | Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof | Ashish Baraskar, Yanli Zhang, Liang Pang, Matthias Baenninger, Yingda Dong | 2017-08-29 |
| 9728551 | Multi-tier replacement memory stack structure integration scheme | Zhenyu Lu, Jixin Yu, Daxin Mao, Johann Alsmeier, Wenguang Shi +1 more | 2017-08-08 |
| 9673216 | Method of forming memory cell film | Ashish Baraskar, Liang Pang, Yingda Dong | 2017-06-06 |
| 9666591 | Non-volatile memory with silicided bit line contacts | Simon S. Chan, Hidehiko Shiraiwa, Lei Xue | 2017-05-30 |