ZS

Zeev Sperber

IN Intel: 15 patents #82 of 5,604Top 2%
Overall (2017): #2,768 of 506,227Top 1%
15
Patents 2017

Issued Patents 2017

Patent #TitleCo-InventorsDate
9772674 Performing local power gating in a processor Nadav Bonen, Ron Gabor, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes +2 more 2017-09-26
9753889 Gather using index array and finite state machine Robert Valentine, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover +1 more 2017-09-05
9716646 Using thresholds to gate timing packet generation in a tracing system Tsvika Kurts, Beeman C. Strong, Ofer Levy, Gabi Malka 2017-07-25
9696997 Real time instruction trace processors, methods, and systems Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Jason W. Brandt 2017-07-04
9678751 Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction Elmoustapha Ould-Ahmed-Vall, Moustapha Hagog, Robert Valentine, Amit Gradstein, Simon Rubanovich +2 more 2017-06-13
9672034 Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits Robert Valentine, Benny Eitan, Doron Orenstein 2017-06-06
9658850 Apparatus and method of improved permute instructions Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more 2017-05-23
9639354 Packed data rearrangement control indexes precursors generation processors, methods, systems, and instructions Seth Abraham, Robert Valentine, Elmoustapha Ould-Ahmed-Vall, Amit Gradstein 2017-05-02
9626333 Scatter using index array and finite state machine Robert Valentine, Shlomo Raikin, Stanislav Shwartsman, Gal Ofir, Igor Yanover +2 more 2017-04-18
9619236 Apparatus and method of improved insert instructions Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more 2017-04-11
9619226 Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction Mostafa Hagog, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Amit Gradstein, Simon Rubanovich 2017-04-11
9606770 Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions Cristina S. Anderson, Simon Rubanovich, Benny Eitan, Amit Gradstein 2017-03-28
9588764 Apparatus and method of improved extract instructions Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more 2017-03-07
9582464 Systems, apparatuses, and methods for performing a double blocked sum of absolute differences Elmoustapha Ould-Ahmed-Vall, Mostafa Hagog, Robert Valentine, Amit Gradstein, Simon Rubanovich 2017-02-28
9542154 Fused multiply add operations using bit masks Simon Rubanovich, Thierry Pons, Amit Gradstein 2017-01-10