| 9841807 |
Method and apparatus for a zero voltage processor sleep state |
Sanjeev Jahagirdar, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh +1 more |
2017-12-12 |
| 9727388 |
Migrating threads between asymmetric cores in a multiple core processor |
Sanjeev Jahagirdar, Inder M. Sodhi |
2017-08-08 |
| 9690353 |
System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request |
Douglas R. Moran, Achmed R. Zahir, William Knolla, Hartej Singh, Vasudev Bibikar +3 more |
2017-06-27 |
| 9626316 |
Managing shared resources between multiple processing devices |
Inder M. Sodhi, Joydeep Ray |
2017-04-18 |
| 9600413 |
Common platform for one-level memory architecture and two-level memory architecture |
Joydeep Ray, Inder M. Sodhi, Jeffrey R. Wilcox |
2017-03-21 |
| 9569278 |
Asymmetric performance multicore architecture with same instruction set architecture |
Sanjeev Jahagirdar, Deborah T. Marr |
2017-02-14 |