Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 9785433 | Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding | Guillem Sole, Manel Fernandez | 2017-10-10 | $9,084,000 |
| 9733935 | Super multiply add (super madd) instruction | Jesus Corbal, Andrew T. Forsyth, Manel Fernandez, Thomas D. Fletcher | 2017-08-15 | $8,272,000 |
| 9654143 | Consecutive bit error detection and correction | Guillem Sole, Sorin Iacobovici, Brian J. Hickmann, Wei Wu, Thomas D. Fletcher | 2017-05-16 | $8,597,000 |
| 9606931 | Indicating a length of an instruction of a variable length instruction set | Santiago Galan, Julio Gago, Jose Gonzalez | 2017-03-28 | $8,391,000 |