Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9785433 | Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding | Roger Espasa, Manel Fernandez | 2017-10-10 |
| 9654143 | Consecutive bit error detection and correction | Roger Espasa, Sorin Iacobovici, Brian J. Hickmann, Wei Wu, Thomas D. Fletcher | 2017-05-16 |