Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842944 | Solid-source diffused junction for fin-based electronics | Walid M. Hafez | 2017-12-12 |
| 9806095 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2017-10-31 |
| 9799668 | Memory cell having isolated charge sites and method of fabricating same | Ting Chang, Walid M. Hafez | 2017-10-24 |
| 9793373 | Field effect transistor structure with abrupt source/drain junctions | Anand S. Murthy, Robert S. Chau, Patrick Morrow, Paul Packan | 2017-10-17 |
| 9786783 | Transistor architecture having extended recessed spacer and source/drain regions and method of making same | Walid M. Hafez, Joodong Park, Jeng-Ya David Yeh, Curtis Tsai | 2017-10-10 |
| 9780217 | Non-planar semiconductor device having self-aligned fin with top blocking layer | Jeng-Ya David Yeh, Walid M. Hafez, Joodong Park | 2017-10-03 |
| 9748327 | Pillar resistor structures for integrated circuitry | Chen-Guan Lee, Walid M. Hafez | 2017-08-29 |
| 9748252 | Antifuse element utilizing non-planar topology | Walid M. Hafez, Curtis Tsai, Joodong Park, Jeng-Ya David Yeh | 2017-08-29 |
| 9741721 | Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM) | Joodong Park, Gopinath Bhimarasetti, Rahul Ramaswamy, Walid M. Hafez, Jeng-Ya David Yeh +1 more | 2017-08-22 |
| 9640634 | Field effect transistor structure with abrupt source/drain junctions | Anand S. Murthy, Robert S. Chau, Patrick Morrow, Paul Packan | 2017-05-02 |
| 9570467 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2017-02-14 |