Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818542 | Gate-all-around fin device | John B. Campi, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2017-11-14 |
| 9704852 | Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode | Tom C. Lee, You Li, Rahul Mishra, Souvick Mitra, Andreas Scholze | 2017-07-11 |
| 9684029 | Transmission line pulse and very fast transmission line pulse reflection control | Shunhua T. Chang, Evan Grund | 2017-06-20 |
| 9620497 | Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers | James P. Di Sarro, Nathan Jack, Junjun Li, Souvick Mitra | 2017-04-11 |
| 9590108 | Gate-all-around fin device | John B. Campi, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2017-03-07 |
| 9575115 | Methodology of grading reliability and performance of chips across wafer | Nathaniel R. Chadwick, James P. Di Sarro, Tom C. Lee, Junjun Li, Souvick Mitra +2 more | 2017-02-21 |
| 9536870 | SCR with fin body regions for ESD protection | James P. Di Sarro, Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam | 2017-01-03 |